1. Field of the Invention
The present invention relates to an ion implantation apparatus and method, and more particularly, to a partial ion implantation apparatus and method using a bundled beam.
2. Description of the Related Art
In general, semiconductor devices, more particularly, semiconductor memory devices such as dynamic random access memories (DRAMs), are manufactured via a great number of unit processes. The unit processes include a lamination process, etching process, ion implantation process, etc. Conventionally, the unit processes are performed for each wafer. Of the above mentioned unit processes, an ion implantation process is a process technique for accelerating dopant ions such as boron and arsenic using a strong electric field, so as to allow the dopant ions to pass through the surface of a wafer. Implantation of such ions is able to change the electrical properties of materials.
When performing the ion implantation process for a wafer, generally, ion beams are scanned in an X-direction while moving the wafer in a Y-direction, so as to implant ions into the wafer. In the implementation of the ion implantation process, it is conventional that approximately the same dose of ions is implanted over the entire region of the wafer. This ion implantation manner is efficient for the ion implantation process itself, but may be undesirable in consideration of other unit processes. That is, where other several unit processes are sequentially performed, the process results, such as the thickness of a laminated film and etching degree, may be irregular over the entire area of the wafer. This is because a number of parameters related to each unit process cannot be accurately controlled. For this reason, it can be said that there always exist process errors due to unexpected or inaccurately controlled process parameters.
For example, in the formation of a gate electrode, a critical dimension (CD), which represents the width of the gate electrode, may be irregular per a specific position on a wafer. Generally, the CD of the gate electrode may be larger at the center of the wafer than that at the edge of the wafer, or vice versa. As stated above, such a difference in the CD is because of a difficulty to accurately control a number of parameters related to the several unit processes. Where the CD of the gate electrode is larger at the center of the wafer than that at the edge of the wafer, a threshold voltage of a resulting device must be larger at the center of the wafer than that at the edge of the wafer. Conversely, where the CD of the gate electrode is larger at the edge of the wafer than that at the center of the wafer, a threshold voltage of a resulting device must be smaller at the center of the wafer than that at the edge of the wafer. The difference in the CD of the gate electrode depending on positions on the wafer may cause a serious problem that is proportional to the degree of integration of devices.